1. Technical Field of the Invention
The invention relates generally to semiconductor-on-insulator devices and methods for forming the same. The invention relates particularly to semiconductor-on-insulator transistors which operate in a fully-depleted mode.
2. Background of the Art
Semiconductor-on-insulator (SOI) transistor devices are typically formed using silicon and generally operate in either a partially-depleted mode or a fully-depleted mode. SOI devices operating in a fully-depleted mode offer good short channel control by having only a thin semiconductor (silicon) film underneath a gate electrode. The thinness of the film physically restrains the short channel effects. In order to achieve this effect, the semiconductor film thickness under the gate may be less than about ⅓ of the gate length. Fully-depleted SOI transistors may also have other advantages over partially-depleted SOI transistors, such as lower subthreshold leakage and more convenient source and drain formation.
However, fully-depleted SOI transistors tend to have high parasitic resistance. This is because of the thin silicon film used in fully-depleted SOI transistors leads to thin silicide formations on the source and drain of the transistors. The thin silicide regions have high electrical resistance, which leads to degraded device performance. The trend toward reduced gate sizes exacerbates the parasitic resistance problem for fully-depleted SOI transistors.
From the foregoing it will be appreciated that a need exists for a fully-depleted SOI transistor which lessens or avoids the high parasitic resistance problem described above.
A fully-depleted semiconductor-on-insulator (SOI) transistor device has an SOI substrate with a buried insulator layer having a nonuniform depth relative to a top surface of the substrate, the buried insulator layer having a shallow portion closer to the top surface than deep portions of the layer. A gate is formed on a thin semiconductor layer between the top surface and the shallow portion of the insulator layer. Source and drain regions are formed on either side of the gate, the source and drain regions each being atop one of the deep portions of the buried insulator layer. The source and drain regions thereby have a greater thickness than the thin semiconductor layer. Thick silicide regions formed in the source and drain regions have low parasitic resistance. A method of making the transistor device includes forming a dummy gate structure on an SOI substrate, and using the dummy gate structure to control the depth of an implantation to form the nonuniform depth buried insulator layer.
According to aspect of the invention, a fully-depleted SOI transistor device has an SOI substrate with a buried insulator layer having a nonuniform depth relative to a top surface of the substrate.
According to another aspect of the invention, an SOI transistor device includes an SOI substrate with a buried insulator layer having a shallow portion which is closer to a surface of the substrate than are deep portions of the buried insulator layer. The transistor device includes a gate atop the shallow portion, with a semiconductor layer therebetween.
According to yet another aspect of the invention, a fully-depleted SOI transistor device includes source and drain regions which are thicker than a semiconductor region beneath a gate.
According to still another aspect of the invention, a fully-depleted SOI transistor device includes a gate, and silicide regions on opposite sides of the gate, the suicide regions having a maximum thickness which is greater than a thickness of a semiconductor region beneath a gate.
According to a further aspect of the invention, a method of forming an SOI substrate with a buried insulator layer which is a nonuniform distance from a top surface of the substrate, includes the steps of forming a structure on the top surface, and implanting ions through the top surface. The resulting buried insulator layer has a shallow portion, relatively close to the top surface, in the vicinity of the structure, and deep portions, relatively far from the top surface, away from the structure.
According to another aspect of the invention, a semiconductor-on-insulator transistor device includes a silicon-on-insulator substrate having a top surface, the substrate including a buried insulator layer and a semiconductor layer, the buried insulator layer having a shallow portion and deep portions, wherein the shallow portion is closer to the top surface than deep portions, and the semiconductor layer being atop the shallow portion; and a gate atop the semiconductor layer.
According to yet another aspect of the invention, a method for manufacturing a semiconductor-on-insulator transistor device, includes the steps of: forming a buried insulator layer having a nonuniform depth relative to a top surface of a semiconductor-on-insulator substrate, the buried insulator layer having a shallow portion closer to the top surface than deep portions of the buried insulator layer; and forming a gate on the substrate over the shallow portion, a semiconductor layer of the substrate thereby being between the gate and the shallow portion.
To the accomplishment of the foregoing and related ends, the invention comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.